JPH0410251B2 - - Google Patents
Info
- Publication number
- JPH0410251B2 JPH0410251B2 JP13660685A JP13660685A JPH0410251B2 JP H0410251 B2 JPH0410251 B2 JP H0410251B2 JP 13660685 A JP13660685 A JP 13660685A JP 13660685 A JP13660685 A JP 13660685A JP H0410251 B2 JPH0410251 B2 JP H0410251B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- inputs
- cmos inverter
- transfer gate
- inverts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Logic Circuits (AREA)
- Information Transfer Systems (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13660685A JPS61294934A (ja) | 1985-06-21 | 1985-06-21 | 半導体装置およびデ−タ伝送路 |
US06/875,551 US4785204A (en) | 1985-06-21 | 1986-06-18 | Coincidence element and a data transmission path |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13660685A JPS61294934A (ja) | 1985-06-21 | 1985-06-21 | 半導体装置およびデ−タ伝送路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61294934A JPS61294934A (ja) | 1986-12-25 |
JPH0410251B2 true JPH0410251B2 (en]) | 1992-02-24 |
Family
ID=15179226
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13660685A Granted JPS61294934A (ja) | 1985-06-21 | 1985-06-21 | 半導体装置およびデ−タ伝送路 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61294934A (en]) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2768872B1 (fr) * | 1997-09-25 | 2000-09-08 | Sgs Thomson Microelectronics | Porte logique ou-exclusif a quatre entrees complementaires deux a deux et a deux sorties complementaires, et multiplieur de frequence l'incorporant |
-
1985
- 1985-06-21 JP JP13660685A patent/JPS61294934A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS61294934A (ja) | 1986-12-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6327176B1 (en) | Single event upset (SEU) hardened latch circuit | |
JPS6359171B2 (en]) | ||
CN108233894B (zh) | 一种基于双模冗余的低功耗双边沿触发器 | |
US5434519A (en) | Self-resetting CMOS off-chip driver | |
JP3502116B2 (ja) | 単一ワイヤクロックを有する2段cmosラッチ回路 | |
US6373310B1 (en) | Scalable set/reset circuit with improved rise/fall mismatch | |
US6181596B1 (en) | Method and apparatus for a RAM circuit having N-Nary output interface | |
JPH0876976A (ja) | Xor回路と反転セレクタ回路及びこれらを用いた加算回路 | |
JPH0683065B2 (ja) | 分周回路 | |
JPH0690163A (ja) | Cmosオフチップ・ドライバ回路 | |
US5994936A (en) | RS flip-flop with enable inputs | |
JPH0410251B2 (en]) | ||
JPH0275219A (ja) | ラッチ回路 | |
JPH0551209B2 (en]) | ||
JPH0441850B2 (en]) | ||
US5291078A (en) | Gate circuits in transition detection input buffers | |
KR100348306B1 (ko) | 레벨쉬프터 | |
JP3012276B2 (ja) | 出力回路 | |
JPS61294932A (ja) | 半導体装置およびデ−タ伝送路 | |
JPH04369920A (ja) | 入力選択機能付きラッチ回路 | |
JPH0521451B2 (en]) | ||
JPS61294931A (ja) | 半導体装置およびデ−タ伝送路 | |
JPH0765577A (ja) | 半導体記憶装置の出力回路 | |
JP2699496B2 (ja) | 出力回路 | |
JPS62231521A (ja) | 半導体集積回路 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |